Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for reducing switching loss. Merely by way of example, some embodiments of the invention have been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.
FIG. 1 is a simplified diagram showing a conventional power conversion system with a rectifying circuit. The power conversion system 100 (e.g., a power converter) includes a rectifying bridge 101, a primary controller 102 (e.g., a chip), a primary winding 104, a secondary winding 106, a secondary controller 108 (e.g., a chip), a diode 109, an auxiliary winding 124, a current sensing resistor 128, capacitors 103, 107, 112, 140 and 142, resistors 105, 122, 126, 132, 146, 148, 150 and 152, a shunt regulator (e.g., TL431) 144, an opto-coupler 171, a capacitor 160, and switches 110 and 130. The primary controller 102 includes a comparator 162, a demagnetization detector 164, and a flip-flop 166. The secondary controller 108 includes comparators 168 and 176, a timer 174 (e.g., a 2-μs leading-edge-blanking timer), and a flip-flop 172.
As shown in FIG. 1, the ground voltage of the primary side is the ground voltage of the chip 102, and the ground voltage of the secondary side is the ground voltage of the chip 108. The ground voltage of the chip 102 is biased to 0 volts, and the ground voltage of the chip 102 is separated from the ground voltage of the chip 108 by at least the opto-coupler 171.
If the switch 130 (e.g., a transistor) is closed (e.g., turned on), the energy is stored in the transformer that includes the primary winding 104 and the secondary winding 106. The transformer generates an output voltage 180, which is received by a voltage divider that includes the resistors 150 and 148. Through the opto-coupler 171, a feedback signal 178 is generated. If the switch 130 is open (e.g., turned off), the stored energy of the transformer is transferred to the secondary side, and a demagnetization process begins. During the demagnetization process, the switch 110 (e.g., a transistor) is closed (e.g., turned on). When the demagnetization process ends, the switch 110 is opened (e.g., turned off), and the series resonance occurs between the primary winding 104 and a parasitic capacitor 199 of the switch 130 (e.g., a transistor).
As shown in FIG. 1, the voltage drop across the parasitic capacitor 199 of the switch 130 is equal to the voltage drop between the drain terminal and the source terminal of the transistor 130. If the voltage drop between the drain terminal and the source terminal of the transistor 130 (e.g., Vds) decreases to a low magnitude (e.g., a local minimum), the switch 130 is closed (e.g., turned on) in order to reduce switching loss and improve system efficiency.
FIG. 2 is a simplified timing diagram for the conventional power conversion system 100. The waveform 202 represents a drive signal 182 as a function of time, the waveform 204 represents a current sensing signal 184 (e.g., VCS) as a function of time, the waveform 206 represents a signal 186 (e.g., INV) as a function of time, and the waveform 208 represents a detection signal 188 (e.g., DEM_on) as a function of time. In addition, the waveform 210 represents a current 190 (e.g., Is) that flows through the secondary winding 106 as a function of time, the waveform 212 represents a voltage (e.g., Vsns) as a function of time, and the waveform 214 represents a drive signal 194 (e.g., an SR_gate signal) as a function of time.
As shown by the waveform 202, during an on-time period T1, the drive signal 182 is at a logic high level and the switch 130 is closed (e.g., turned on). When the switch 130 is closed (e.g., turned on), a current 196 flows through the primary winding 104, the switch 130, and the resistor 128, and generates the current sensing signal 184 (e.g., VCS). As shown by the waveform 204, the current sensing signal 184 (e.g., VCS) increases from a value 216 to a value 218 during the on-time period T1. As shown by the waveform 214, on the secondary side of the power conversion system 100, the drive signal 194 is at a logic low level and the switch 110 is open (e.g., turned off) during the on-time period T1. As shown by the waveform 212, the voltage signal 192 (e.g., Vsns) remains at a value 224 during the on-time period T1.
As shown by the waveform 202, at the beginning time to of an off-time period T2, the drive signal 182 changes from the logic high level to the logic low level, and the switch 130 is opened (e.g., turned off) during the off-time period T2. As shown by the waveform 204, at the beginning time to of an off-time period T2, the current sensing signal 184 (e.g., VCS) decreases rapidly from the value 218 to the value 216. As shown by the waveform 206, at the beginning time to of the off-time period T2, the voltage signal 186 (e.g., INV) associated with the auxiliary winding 124 increases rapidly from a value 228 to a value 230. As shown by the waveform 212, at the beginning time to of the off-time period T2, the voltage signal 192 (e.g., Vsns) decreases rapidly from the value 224 to a value 226. For example, the value 224 is higher than zero volts, and the value 226 is lower than zero volts.
As shown by the waveform 210, the current 190 (e.g., Is) increases rapidly from a value 222 at the time t0 to a value 220 at a time t1. As shown by the waveform 214, at the time t1 of the off-time period T2, the drive signal 194 changes from the logic low level to the logic high level, and the switch 110 is closed (e.g., turned on). As shown by the waveform 212, at the time t1 of the off-time period T2, the voltage signal 192 (e.g., Vsns) increases from the value 226 to a value 232. For example, the value 232 is lower than zero volts. As shown by the waveform 206, from the time to to a time t2 of the off-time period T2, the voltage signal 186 (e.g., INV) associated with the auxiliary winding 124 remains approximately at the value 230.
As shown by the waveform 214, from the time t1 to the time t2 of the off-time period T2 (e.g., during a time period T4), the drive signal 194 remains at the logic high level, and the switch 110 remains closed (e.g., turned on). As shown by the waveform 212, from the time t1 to the time t2 of the off-time period T2 (e.g., during the time period T4), the voltage signal 192 (e.g., Vsns) increases gradually from the value 232 to a value 234. For example, the value 234 is equal to −12 mV. As shown by the waveform 210, from the time t1 to the time t2 of the off-time period T2 (e.g., during the time period T4), the current 190 (e.g., Is) decreases from the value 220 to the value 222. For example, the value 222 is close to (e.g., equal to) zero amps. In another example, at the time t2, the demagnetization process ends.
Referring to FIG. 1, at the time t2 of the off-time period T2 (e.g., at the end of the demagnetization process), the comparator 168 outputs a comparison signal 191 to the flip-flop 172 (e.g., the “R” terminal of the flip-flop 172). As shown by the waveform 214, at the time t2 of the off-time period T2, the drive signal 194 changes from the logic high level to the logic low level, and the switch 110 becomes open (e.g., turned off). For example, the time t2 is the beginning time of a time period T5.
As shown by the waveform 206, from the beginning time t2 of the time period T5 to the time t3, series resonance occurs between the primary winding 104 and the parasitic capacitor 199 of the switch 130, and the voltage signal 186 (e.g., INV) associated with the auxiliary winding 124 decreases until the voltage signal 186 reaches a minimum value 239 (e.g., at t3).
As shown by the waveform 208, at the time t3, the demagnetization detector 164 generates a pulse in the signal 188 (e.g., DEM_on). In response to the pulse, as shown by the waveform 202, at the time t3, the drive signal 182 changes from the logic low level to the logic high level, and the switch 130 is closed (e.g., turned on). For example, the time t3 is the beginning of another on-time period T3 for the drive signal 182.
As shown in FIGS. 1 and 2, the turn-on voltage of the switch 130 is determined as follows:Vturn_on=Vin−N×V0  (Equation 1)where Vturn_on, represents the turn-on voltage of the switch 130, Vin represents an input voltage 198, N represents a turns ratio between the primary winding 104 and the secondary winding 106, and Vo represents the output voltage 180.
According to Equation 1, the turn-on voltage of the switch 130 increases with the input voltage 198, so the turn-on voltage of the switch 130 is higher at high input voltage than at low input voltage. Also, the switching frequency of the conventional power conversion system 100 (e.g., a quasi-resonant power converter) is higher at high input voltage than at low input voltage. Therefore, at high input voltage, switching loss of the conventional power conversion system 100 often is significantly larger than that at low input voltage. Such switching loss at high input voltage can severely adversely affect the system efficiency.
To reduce the switching loss, a delay can be introduced between the end of the demagnetization process and the turning-off of the switch 110. FIG. 3 is a simplified conventional timing diagram for another power conversion system. The waveform 302 represents a drive signal on the primary side as a function of time, the waveform 304 represents a current sensing signal (e.g., VCS) as a function of time, the waveform 305 represents a current that flows through the primary winding (e.g., Iin) as a function of time, the waveform 306 represents another drive signal (e.g., an SR_gate signal) on the secondary side as a function of time, the waveform 308 represents a current that flows through a secondary winding as a function of time, and the waveform 310 represents a voltage drop on a switch on the primary side as a function of time. For example, the switch on the primary side is a transistor, and the voltage drop on the switch is the voltage drop between the drain terminal and the source terminal of the transistor (e.g., Vds).
As shown in FIG. 3, the time t11 represents the end time of the demagnetization process, and the time t12 represents the time when the another drive signal (e.g., the SR_gate signal) changes from the logic high level to the logic low level and the switch on the secondary side becomes opened (e.g., turned off). From the time t11 to the time t12, there is a delay as indicated by the time period Td.
However, the conventional power conversion systems have various disadvantages. Hence it is highly desirable to improve the techniques of reducing switching loss of power conversion systems.